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ADT7475
functionality can be changed (see the Disabling Fan Startup
Timeout section).
Table 35. PWM1 TO PWM3 CONFIGURATION
(REG. 0X5C TO 0X5E)
Bit Mnemonic Description
<2:0> SPIN These bits control the startup
timeout for PWM1 (0x5C),
PWM2 (0x5D), PWM3 (0x5E).
000 = No Startup Timeout
001 = 100 ms
010 = 250 ms (Default)
011 = 400 ms
100 = 667 ms
101 = 1 s
110 = 2 s
111 = 4 s
Disabling Fan Startup Timeout
Although fan startup makes fan spin-ups much quieter
than fixed-time spin-ups, the option exists to use fixed
Fan Speed Control
The ADT7475 controls fan speed using automatic mode
and manual mode as follows:
? In automatic fan speed control mode, fan speed is
automatically varied with temperature and without CPU
intervention, once initial parameters are set up. The
advantage of this is, if the system hangs, the user is
guaranteed that the system is protected from overheating.
For more information about how to program
the automatic fan speed control loop, see the
Programming the Automatic Fan Speed Control Loop
section.
? In manual fan speed control mode, the ADT7475 allows
the duty cycle of any PWM output to be manually
adjusted. This can be useful if the user wants to change
fan speed at the software level or adjust PWM duty
cycle output for test purposes. Bits <7:5> of
Register 0x5C to Register 0x5E (PWM configuration)
control the behavior of each PWM output.
spin-up times. Setting Bit 5 (FSPDIS) to 1 in Configuration
Register 1 (0x40) disables the spin-up for two TACH pulses.
Instead, the fan spins up for the fixed time as selected in
Register 0x5C to Register 0x5E.
Table 38. PWM CONFIGURATION
(REG. 0X5C TO 0X5E) BITS
Bit Mnemonic
Description
PWM Logic State
<7:5>
BHVR 111
Manual Mode
The PWM outputs can be programmed high for 100%
duty cycle (non-inverted) or low for 100% duty cycle
(inverted).
Table 36. PWM1 TO PWM3 CONFIGURATION
(REG. 0X5C TO 0X5E) BITS
Once under manual control, each PWM output can be
manually updated by writing to Register 0x30 to
Register 0x32 (PWMx current duty cycle registers).
Programming the PWM Current Duty Cycle Registers
The PWM current duty cycle registers are 8-bit registers
Bit
<4>
Mnemonic
INV
Description
0 = logic high for 100% PWM duty cycle
1 = logic low for 100% PWM duty cycle
that allow the PWM duty cycle for each output to be set
anywhere from 0% to 100% in steps of 0.39%.
The value to be programmed into the PWM MIN register is
given by:
Low Frequency Mode PWM Drive Frequency
The PWM drive frequency can be adjusted for the
application. Register 0x5F to Register 0x61 configure the
PWM frequency for PWM1 to PWM3, respectively. In high
frequency mode, the PWM drive frequency is always
22.5 kHz.
High Frequency Mode PWM Drive
Setting Bit 3 of Register 0x5F, Register 0x60, and
Register 0x61 enables high frequency mode for Fan 1,
Fan 2, and Fan 3, respectively.
Table 37. PWM FREQUENCY REGISTERS
Value (decimal) = PWM MIN /0.39
Example 1:
For a PWM duty cycle of 50%,
Value (decimal) = 50/0.39 = 128 (decimal)
Value = 128 (decimal) or 0x80 (hex)
Example 2:
For a PWM duty cycle of 33%,
Value (decimal) = 33/0.39 = 85 (decimal)
Value = 85 (decimal) or 0x54 (hex)
Table 39. PW M CURRENT DUTY CYCL E REGISTERS
(REG. 0X5F TO 0X61)
Register
Description
Default
Bit
Mnemonic
Description
0x30
PWM1 Current Duty Cycle
0x00 (0%)
<2:0>
FREQ
000 = 11.0 Hz
001 = 14.7 Hz
010 = 22.1 Hz
011 = 29.4 Hz
100 = 35.3 Hz (Default)
101 = 44.1 Hz
110 = 58.8 Hz
111 = 88.2 Hz
0x31 PWM2 Current Duty Cycle 0x00 (0%)
0x32 PWM3 Current Duty Cycle 0x00 (0%)
By reading the PWMx current duty cycle registers, the
user can keep track of the current duty cycle on each PWM
output, even when the fans are running in automatic fan
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